The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 2009
Filed:
Apr. 16, 2007
Kwang Young Kim, Irvine, CA (US);
Josephus A. E. P. Van Engelen, Aliso Viejo, CA (US);
Kwang Young Kim, Irvine, CA (US);
Josephus A. E. P. Van Engelen, Aliso Viejo, CA (US);
Broadcom Corporation, Irvine, CA (US);
Abstract
A power-down biasing circuit includes a current source connected to a drain of a first NMOS transistor through a first switch. A gate of the first NMOS transistor is connected to the current source, and a source of the first NMOS transistor is connected to ground. A first pre-chargeable capacitor is connected between the gate of the first NMOS transistor and ground. A plurality of NMOS transistors form a current multiplier and have gates connected to the current reference. A plurality of current mirrors are connected to drains of the plurality of NMOS transistors and to output switches. Each current mirror has a first PMOS transistor whose drain is connected to a drain of a corresponding one of the plurality of NMOS transistors through a second switch, whose gate is connected to the drain of the corresponding one of the plurality of NMOS transistors and whose source is connected to a supply voltage; a second capacitor is connected between the gate of the first PMOS transistor and the supply voltage; and at least two PMOS transistors are connected as a current multiplier to the output switches. Cascode equivalent biasing circuits are described also.