The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2009

Filed:

Dec. 01, 2003
Applicants:

Toshitsugu Sakamoto, Tokyo, JP;

Hisao Kawaura, Tokyo, JP;

Toshio Baba, Tokyo, JP;

Fumiyuki Nihey, Tokyo, JP;

Yukinori Ochiai, Tokyo, JP;

Hiroo Hongo, Tokyo, JP;

Inventors:

Toshitsugu Sakamoto, Tokyo, JP;

Hisao Kawaura, Tokyo, JP;

Toshio Baba, Tokyo, JP;

Fumiyuki Nihey, Tokyo, JP;

Yukinori Ochiai, Tokyo, JP;

Hiroo Hongo, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

There has been a problem that micromiaturization causes increase of the resistance of wiring structure and degradation of electron migration resistance and stress migration resistance. The present invention provides a wiring structure of a semiconductor device having a low resistance even when the semiconductor device is microminiaturized, free of electron migration and stress migration, and having a high reliability and a method for manufacturing the same. A semiconductor device having a wiring or a connection plug made of a mixture of a metal and carbon nanotubes berried in a wiring groove or a via hole made in an insulating film on a substrate where a semiconductor chip is fabricated, and its manufacturing method are provided.


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