The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2009

Filed:

Nov. 15, 2004
Applicants:

Koji Otsuka, Niiza, JP;

Masataka Yanagihara, Niiza, JP;

Nobuo Kaneko, Niiza, JP;

Inventors:

Koji Otsuka, Niiza, JP;

Masataka Yanagihara, Niiza, JP;

Nobuo Kaneko, Niiza, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/207 (2006.01);
U.S. Cl.
CPC ...
Abstract

A substrate system of the kind having a buffer region interposed between a silicon substrate proper and a nitride semiconductor region in order to make up for a difference in linear expansion coefficient therebetween. Electrodes are formed on the nitride semiconductor layer or layers in order to provide HEMTs or MESFETs. The buffer region is a lamination of a multiplicity of buffer layers each comprising a first, a second, and a third buffer sublayer of nitride semiconductors, in that order from the silicon substrate proper toward the nitride semiconductor region. The three sublayers of each buffer layer contain aluminum in varying proportions including zero. The aluminum proportion of the third buffer sublayer is either zero or intermediate that of the first buffer sublayer and that of the second. The low aluminum proportion of the third buffer sublayer serves to prevent two-dimensional electron gas from generating in the buffer region and hence to make this region sufficiently high in resistance to inhibit current leakage from the HEMTs or MESFETs.


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