The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2009

Filed:

Sep. 08, 2006
Applicants:

Ramachandran Muralidhar, Austin, TX (US);

Rajesh A. Rao, Austin, TX (US);

Michael A. Sadd, Mountain View, CA (US);

Bruce E. White, Round Rock, TX (US);

Inventors:

Ramachandran Muralidhar, Austin, TX (US);

Rajesh A. Rao, Austin, TX (US);

Michael A. Sadd, Mountain View, CA (US);

Bruce E. White, Round Rock, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.


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