The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2009
Filed:
Jul. 11, 2006
Chong Ming Lin, Sunnyvale, CA (US);
Tatao Chuang, San Jose, CA (US);
Tran Long, San Jose, CA (US);
Hy Hoang, San Jose, CA (US);
Chong Ming Lin, Sunnyvale, CA (US);
Tatao Chuang, San Jose, CA (US);
Tran Long, San Jose, CA (US);
Hy Hoang, San Jose, CA (US);
Seiko Epson Corporation, , JP;
Abstract
A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. A height and width for the power bus is calculated based on its coordinates. Based on the height and width of the power buses and the predetermined size and spacing between power slits, a number of power slits to be generated is determined. These power slits are then generated by adding the power slits to the power bus in the coordinates of the layout database. The method of the present invention also generates power slits for use in manufacturing power buses on a chip for cases in which the power buses overlap.