Test semiconductor device in full frequency with half frequency tester

Abstract

An integrated circuit comprises a double frequency clock generator and a double input generator to test semiconductor devices at frill frequency using a half frequency tester. A clock generator circuit and a test data generator circuit provides differential clock and test data signals at a normal (1× mode) and high-speed rate (2× mode) to a device under test. In 1× mode, clock generator and test data generator circuits pass through the differential clock signals and test data values provided by a testing device unchanged. In 2× mode, the clock generator circuit receives the differential clock signal as clock signals clk and clkb and outputs clock signals clk_int and clkb_int that are inverted signals and twice the frequency of clk and clkb. The test data generator circuit clocks test data values into registers according to clk_int and clkb_int to generate an increased number of test data values per clock signal clk.