The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2009

Filed:

Feb. 17, 2004
Applicants:

Alireza Moini, Balmain, AU;

Kia Silverbrook, Balmain, AU;

Paul Lapstun, Balmain, AU;

Peter Charles Boyd Henderson, Balmain, AU;

Zhenya Alexander Yourlo, Balmain, AU;

Matthew John Underwood, Balmain, AU;

Nicholas Damon Ridley, Balmain, AU;

Inventors:

Alireza Moini, Balmain, AU;

Kia Silverbrook, Balmain, AU;

Paul Lapstun, Balmain, AU;

Peter Charles Boyd Henderson, Balmain, AU;

Zhenya Alexander Yourlo, Balmain, AU;

Matthew John Underwood, Balmain, AU;

Nicholas Damon Ridley, Balmain, AU;

Assignee:

Silverbrook Research Pty Ltd, Balmain, New South Wales, AU;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N 3/14 (2006.01); H04N 5/335 (2006.01); H01L 27/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A photodetecting circuit comprising a photodetector for generating a signal in response to incident light; a storage node having first and second node terminals, the first node terminal being connected to the photodetector to receive the signal such that charge stored in the node changes during an integration period of the photodetecting circuit; and an output circuit for generating an output signal during a read period of the photodetecting circuit, the output signal being at least partially based on a voltage at the first terminal; the photodetecting circuit being configured to receive a reset signal; integrate charge in the storage node during an integration period following receipt of the reset signal; and receive a compensation signal at the second terminal of the storage node at least during the read period, the compensation signal increasing the voltage at the first terminal whilst the output circuit generates the output signal.


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