The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2009

Filed:

Aug. 18, 2006
Applicants:

Suk-pil Kim, Yongin-si, KR;

Jae-woong Hyun, Uijeongbu-si, KR;

Yoon-dong Park, Yongin-si, KR;

Won-joo Kim, Suwon-si, KR;

Dong-gun Park, Seongnam-si, KR;

Choong-ho Lee, Seongnam-si, KR;

Inventors:

Suk-Pil Kim, Yongin-si, KR;

Jae-Woong Hyun, Uijeongbu-si, KR;

Yoon-Dong Park, Yongin-si, KR;

Won-Joo Kim, Suwon-si, KR;

Dong-Gun Park, Seongnam-si, KR;

Choong-Ho Lee, Seongnam-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

Example embodiments of the present invention relate to a semiconductor device and methods of fabricating the same. Other example embodiments of the present invention relate to a fin-field effect transistor (Fin-FET) having a fin-type channel region and methods of fabricating the same. A Fin-FET having a gate all around (GAA) structure that may use an entire area around a fin as a channel region is provided. The Fin-FET having the GAA structure includes a semiconductor substrate having a body, a pair of support pillars and a fin. The pair of support pillars may protrude from the body. A fin may be spaced apart from the body and may have ends connected to and supported by the pair of support pillars. A gate electrode may surround at least a portion of the fin of the semiconductor substrate. The gate electrode may be insulated from the semiconductor substrate. A gate insulation layer may be interposed between the gate electrode and the fin of the semiconductor substrate.


Find Patent Forward Citations

Loading…