The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2009

Filed:

Feb. 24, 2006
Applicants:

Mikio Izumi, Yokohama, JP;

Toshifumi Hayashi, Yokohama, JP;

Shigeru Odanaka, Yokohama, JP;

Hirotaka Sakai, Machida, JP;

Naotaka Oda, Yokohama, JP;

Toshifumi Sato, Tama, JP;

Toshiaki Ito, Kawasaki, JP;

Inventors:

Mikio Izumi, Yokohama, JP;

Toshifumi Hayashi, Yokohama, JP;

Shigeru Odanaka, Yokohama, JP;

Hirotaka Sakai, Machida, JP;

Naotaka Oda, Yokohama, JP;

Toshifumi Sato, Tama, JP;

Toshiaki Ito, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A verification method is provided for verifying a safety apparatus including a programmable logic device having a plurality of functional elements. The verification method includes the steps of exhaustively verifying the plurality of functional elements on actual hardware, generating a functional element that is the same as one of the functional elements verified on the actual apparatus using a predetermined hardware description language, independently logic-synthesizing each generated functional element into a plurality of first net lists, generating a connection function between the functional elements using the predetermined hardware description language, logic-synthesizing the generated connection function into a second net list corresponding to the connection function, synthesizing the first net lists with the second net list to generate a third net list, writing a logic circuit into the programmable logic device on the basis of the third net list, and verifying the actual programmable logic device.


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