The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 31, 2009
Filed:
Mar. 18, 2005
Jamshid Foroudian, Campbell, CA (US);
John S. OH, San Jose, CA (US);
Jamshid Foroudian, Campbell, CA (US);
John S. Oh, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A multi-phase-locked loop (PLL) solution is described for multi-link multi-rate line cards. A reconfigurable enhanced phase-locked loop (EPLL) associated with a particular port in a line card is cascaded with an fast phase-locked loop (FPLL) and their combined output is used to provide a sampling clock to a data handler such as a serializer/deserializer (SERDES). The enhanced phase-locked loop (EPLL) is operable to take a multi-rate clock input and scale it accordingly to provide a fixed rate clock to the fast phase-locked loop (FPLL) input. The enhanced phase-locked loop (EPLL) can be dynamically reconfigured without affecting operation of other ports in the line card. The fast phase-locked loop (FPLL) and serializer/deserializer (SERDES) sample link data at a fixed rate and pass the data down through the communication system.