Mis-transistor-based nonvolatile memory with reliable data retention capability

Abstract

A nonvolatile semiconductor memory device includes a nonvolatile memory cell including an odd number of MIS transistor pairs, each of which stores one-bit data by creating an irreversible change of transistor characteristics in one of the two paired MIS transistors, latches equal in number to the odd number of MIS transistor pairs to store the odd number of one-bit data recalled from the MIS transistor pairs, the recalling of the one-bit data of a given MIS transistor pair being performed by sensing a difference in the transistor characteristics between the two paired MIS transistors of the given MIS transistor pair, and a majority decision circuit configured to make a majority decision based on the odd number of one-bit data to determine a bit value of the nonvolatile memory cell.