The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2009

Filed:

Aug. 30, 2006
Applicants:

Hiroshi Suzuki, Sagamihara, JP;

Hiromi Matsushige, Hiratsuka, JP;

Masato Ogawa, Chigasaki, JP;

Inventors:

Hiroshi Suzuki, Sagamihara, JP;

Hiromi Matsushige, Hiratsuka, JP;

Masato Ogawa, Chigasaki, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11B 19/20 (2006.01);
U.S. Cl.
CPC ...
Abstract

A storage system capable of reducing the start-up time of disk drives is provided. If a power source monitor circuit itself is normal (S), the power source monitor circuit reads a detection signal from a detection circuit, and checks power sources (S). If the power sources are normal (S), all disks are spun up (S). When the spin-up of all disks is completed (S), processing is completed. If either of two power sources fails (S), the power source monitor circuit reports the fact to a host control logical part (S). The power source monitor circuit clears its internal counter to zero (S) and issues a drive command to HDDs (S). When the spin-up of all disks is completed (S), processing is completed. If there is a disk which has not yet been spun up, the power source monitor circuit sets the internal counter to n+1 (S) and returns to Step S. N-number of HDDs are divided into groups respectively including six disks, six disks, four disks and one disk, and if the disks are driven in units of the groups, the power source monitor circuit sets the internal counter to n+Δn.


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