The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 31, 2009
Filed:
Mar. 31, 2005
Henry C. Kancler, Los Altos Hills, CA (US);
Tsi-pin Choong, Los Altos Hills, CA (US);
Barry A. Wealand, San Jose, CA (US);
Leon K. Wood, Sunnyvale, CA (US);
Katarina Van Heusen, Menlo Park, CA (US);
John T. Reagan, Santa Clara, CA (US);
Theodore J. Mills, Cupertino, CA (US);
Michael A. Levin, Half Moon Bay, CA (US);
Henry C. Kancler, Los Altos Hills, CA (US);
Tsi-Pin Choong, Los Altos Hills, CA (US);
Barry A. Wealand, San Jose, CA (US);
Leon K. Wood, Sunnyvale, CA (US);
Katarina Van Heusen, Menlo Park, CA (US);
John T. Reagan, Santa Clara, CA (US);
Theodore J. Mills, Cupertino, CA (US);
Michael A. Levin, Half Moon Bay, CA (US);
Lockheed Martin Corporation, Bethesda, MD (US);
Abstract
A system and method for three-axis stabilization of focal plane data. The system and method include performing a two-dimensional vertical shear transformation and a two-dimensional horizontal shear transformation. The system and method further incorporate a SIMD computer architecture and an array of addressable processing elements that process the field-of-view for a target image received by a focal plane array of detector elements. Each processing element includes a calculation device that calculates the row and column address of virtual pixels for a virtual field-of-view. The system and method further include a plurality of memory modules configured to store data in a plurality of addressable storage locations by column and row, and each memory module is identified with a different processing element. A dedicated memory routing network for the processing elements and memory modules permits the exchange of information between processing elements and memory modules associated with each processing element.