The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2009

Filed:

Jun. 15, 2006
Applicants:

Shahid Ali, Bangalore, IN;

Satheesh Balasubramanian, Bangalore, IN;

Sujan Manobar, Karnataka, IN;

Inventors:

Shahid Ali, Bangalore, IN;

Satheesh Balasubramanian, Bangalore, IN;

Sujan Manobar, Karnataka, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03L 5/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method, apparatus and/or system of a level shifter circuit having a structure to reduce fall and rise path delay is disclosed. In one embodiment, a level shifter circuit comprise a first set of sequentially coupled pull-up and pull-down sub-circuits cross coupled to a second set of sequentially pull-up and pull-down sub-circuits to generate a positive feedback loop; an output node coupled to a shared node between the first pull-up and pull-down sub-circuits through an output inverter; a pull-up NMOS transistor with a gate contact coupled to the input of the second set, a source contact coupled to an input of the output inverter and a drain contact coupled to the output voltage of the level shifter circuit; and a pull-down NMOS transistor with a gate contact coupled to the input of the second set, a drain contact coupled to an output of the output inverter and a source contact coupled to a ground.


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