The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 31, 2009
Filed:
Dec. 14, 2006
Serafino Bueti, Waterbury, VT (US);
Hayden C. Cranford, Jr., Cary, NC (US);
Joseph A. Iadanza, Hinesburg, VT (US);
Pradeep Thiagarajan, South Burlington, VT (US);
Sebastian T. Ventrone, South Burglington, VT (US);
Serafino Bueti, Waterbury, VT (US);
Hayden C. Cranford, Jr., Cary, NC (US);
Joseph A. Iadanza, Hinesburg, VT (US);
Pradeep Thiagarajan, South Burlington, VT (US);
Sebastian T. Ventrone, South Burglington, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.