The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2009

Filed:

Feb. 27, 2006
Applicants:

Hugh Sungki O, Fremont, CA (US);

Chih-ching Shih, Pleasanton, CA (US);

Cheng-hsiung Huang, Cupertino, CA (US);

Yow-juang Bill Liu, San Jose, CA (US);

Inventors:

Hugh Sungki O, Fremont, CA (US);

Chih-Ching Shih, Pleasanton, CA (US);

Cheng-Hsiung Huang, Cupertino, CA (US);

Yow-Juang Bill Liu, San Jose, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0175 (2006.01);
U.S. Cl.
CPC ...
Abstract

Circuits, methods, and apparatus for output devices having parasitic transistors for a higher output current drive. One such MOS output device includes a parasitic bipolar transistor that assists output voltage transitions. The parasitic transistor may be inherent in the structure of the MOS device. Alternately, one or more regions, such as implanted or diffused regions, may be added to the MOS device to form or enhance the parasitic bipolar device. The parasitic transistor is turned on when during an appropriate output transition and turned off once the transition is complete. The parasitic device may be turned on by injecting current into the bulk of a pull-down device, by pulling current out of the bulk of a pull-up device, or by tying the bulk of the output device to an appropriate voltage, such as VCC for a pull-down device or ground for a pull-up device.


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