The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 31, 2009
Filed:
Jan. 28, 2008
Keita Takahashi, Nara, JP;
Keita Takahashi, Nara, JP;
Panasonic Corporation, Osaka, JP;
Abstract
The fabrication method for a nonvolatile semiconductor memory device having a memory cell area including memory cells and a peripheral circuit area adjacent to the memory cell area and including peripheral transistors, the method including the steps of: (1) forming a first active region in the memory cell area and a second active region in the peripheral circuit area in a substrate by forming isolation insulating films in the memory cell area and the peripheral circuit area so as to be away from a boundary therebetween; (2) forming a bottom insulating film and an intermediate charge trap film sequentially over the entire surface of the substrate; (3) removing a portion of the intermediate charge trap film formed in the peripheral circuit area using a first mask film; (4) forming a gate insulating film in the peripheral circuit area and also at least part of a top insulating film in the memory cell area; (5) forming a gate electrode film on the top insulating film and the gate insulating film; and (6) forming gate electrodes of memory cells and peripheral transistors by patterning the gate electrode film. The step (3) includes a step of aligning an end of the first mask film with the boundary in the substrate.