Post-logic isolation of silicon regions for an integrated sensor

Abstract

In producing an integrated sensor, regions of silicon between compensating electronics and a sensor are electrically isolated, while the sensor is delineating and released. The described process can be performed at the end of a fabrication process after electronics processing (i.e., CMOS processing) and compensating electronics are formed. In an aspect, the sensor and a conductive bridge are simultaneously developed from a silicon-on-insulator (SOI) substrate. In an aspect, the sensor is undercut from a silicon substrate utilizing a lateral etch. A cavity is concurrently defined by the same lateral etch in the silicon layer, forming the conductive bridge connecting the sensor to a logic component. An isolation trench is defined in the silicon layer between the sensor components and the logic component. A polymer masks vertical surfaces from the lateral etch, and an insulator layer and photosensitive film mask horizontal surfaces from the lateral etch.