The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 24, 2009
Filed:
Mar. 15, 2006
Risako Uchida, Tokyo, JP;
Risako Uchida, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
There is provided an integrated circuit layout design method capable of performing LVS verification in an early stage of layout design. Placement and routing means provides wiring and outputs a layout in which short circuits are possibly left uncorrected. Short-circuit correcting means performs rewiring by using a newly defined tentative wiring layer in which short-circuit wiring portions are removed and outputs an inter-layer method for interconnecting the tentative wiring layer and the original wiring layer to an inter-layer connection information file. Layout verification means uses the corrected layout and an LVS rule file in which the inter-layer connection method is reflected to perform LVS on the layout in which the short circuit portions are modified to correct connections through use of the tentative wiring layer.