The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 24, 2009
Filed:
Jan. 31, 2007
Jin-fa Lin, Chiayi County, TW;
Yin-tsung Hwang, Yunlin County, TW;
Ming-hwa Sheu, Yunlin County, TW;
Cheng-che Ho, Taipei, TW;
Jin-Fa Lin, Chiayi County, TW;
Yin-Tsung Hwang, Yunlin County, TW;
Ming-Hwa Sheu, Yunlin County, TW;
Cheng-Che Ho, Taipei, TW;
National Yunlin University of Science and Technology, Yunlin County, TW;
Abstract
In a full-adder of complementary carry logic voltage compensation, two input terminals of a first multiplexer are connected to a carry input and a carry inverted phase input respectively; an add signal is connected to a select signal; an input terminal of a first inverter is connected to an output signal of the first multiplexer. Two input terminals of a second multiplexer output an addend and a summand; an output signal of the first inverter is selected; an output terminal of the second multiplexer produces a carry signal; an input terminal of the second inverter is connected to an output signal of the second multiplexer for producing a carry inverted phase signal; two input terminals of a third multiplexer input the summand and carry inverted phase signal; an output signal of the first inverter is a select signal; and an output terminal of the third multiplexer produces a sum signal.