The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2009

Filed:

Feb. 24, 2005
Applicants:

Tomoyuki Taguchi, Kusatsu, JP;

Yoshinori Mekata, Moriyama, JP;

Shunichi Komatsu, Kouga-gun, JP;

Hiroki Nishiyama, Hikone, JP;

Tsukasa Iwami, Ohmihachiman, JP;

Inventors:

Tomoyuki Taguchi, Kusatsu, JP;

Yoshinori Mekata, Moriyama, JP;

Shunichi Komatsu, Kouga-gun, JP;

Hiroki Nishiyama, Hikone, JP;

Tsukasa Iwami, Ohmihachiman, JP;

Assignees:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/00 (2006.01); G01R 31/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and a device for testing an array substrate for a liquid crystal display that allow time for testing to be reduced are provided. An array substrate is divided into two test blocks, and two scanning signal lines in total, one from each of the test blocks, are selected and tested at a time, so that the addresses of possible defective pixels are specified. Then, the array substrate is divided into three test blocks, and three scanning signal lines in total, one from each of the test blocks, are selected and re-tested at a time, so that the addresses of possible defective pixels are specified. Then, the address of a pixel common between the first testing and re-testing is specified as a defective address.


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