The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2009

Filed:

Jun. 07, 2006
Applicant:

IN Gyun Jeon, Gunpo-si, KR;

Inventor:

In Gyun Jeon, Gunpo-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/113 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of fabricating a CMOS image sensor is provided. The fabricating method includes: forming a gate electrode with a gate insulating layer interposed at a transistor region of a semiconductor substrate having an active region defined by a photodiode region and a transistor region; forming a first impurity region of a first conductive type at the transistor region of one side of the gate electrode; forming a first sidewall and a second sidewall at both sides of the gate electrode; forming a second impurity region of the first conductive type at the transistor region of the one side of the gate electrode; applying a photoresist layer on the semiconductor substrate, and patterning the photoresist layer to cover the transistor region through an exposing and developing process; forming a third impurity region of a second conductive type at the photodiode region using the patterned photoresist as a mask; selectively removing the first sidewall insulating layer between the second sidewall insulating layer and the gate electrode at a predetermined thickness using the patterned photoresist layer as a mask; covering the gate electrode by reflowing the patterned photoresist layer at a predetermined temperature; selectively removing the second sidewall insulating layer using the reflowed photoresist layer as a mask; and forming a fourth impurity region of the first conductive type at the side of the gate electrode where the third impurity region is formed using the reflowed photoresist layer as a mask.


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