Programmable logic device design tool with support for variable predriver power supply levels

Abstract

A logic design system is provided for designing programmable logic device integrated circuits with minimized predriver power consumption. The logic design system identifies predriver circuits that can operate satisfactorily at reduced predriver power supply levels. One or more reduced predriver power supply levels for powering the predriver circuits are identified by the logic design system. The predriver power supply levels that are identified can be different than a maximum allowable power supply voltage used for powering input-output circuitry on the programmable logic device integrated circuit. There may be multiple blocks of predriver circuitry, each of which is powered using a potentially different predriver power supply voltage. The logic design system uses on-screen options to accept user-supplied settings related to minimizing predriver power consumption.