The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2009

Filed:

Oct. 14, 2005
Applicants:

Robert Glen Gerowitz, Raleigh, NC (US);

Kenichi Tsuchiya, Cary, NC (US);

Inventors:

Robert Glen Gerowitz, Raleigh, NC (US);

Kenichi Tsuchiya, Cary, NC (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/30 (2006.01); G11C 29/54 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system for at-functional-clock-speed continuous scan array built-in self testing (ABIST) of multiport memory is disclosed. During ABIST testing, functional addressing latches from a first port are used as shadow latches for a second port's addressing latches. The arrangement reduces the amount of test-only hardware on a chip and reduces the need to write complex testing software. Higher level functions may be inserted between the shadow latches and the addressing latches to automatically provide functions such as inversions.


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Gerowitz, Robert. (2009). Scanned memory testing of multi-port memory arrays (U.S. Patent No. 7506225). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7506225

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