The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2009

Filed:

May. 20, 2004
Applicants:

Peter Irma August Barri, Bonheiden, BE;

Jean Louis Calvignac, Cary, NC (US);

Kent Harold Haselhorst, Byron, MN (US);

Marco C. Heddes, Cary, NC (US);

Joseph Franklin Logan, Raleigh, NC (US);

Fabrice Jean Verplanken, La Gaude, FR;

Miroslav Vrana, Gent, BE;

Inventors:

Peter Irma August Barri, Bonheiden, BE;

Jean Louis Calvignac, Cary, NC (US);

Kent Harold Haselhorst, Byron, MN (US);

Marco C. Heddes, Cary, NC (US);

Joseph Franklin Logan, Raleigh, NC (US);

Fabrice Jean Verplanken, La Gaude, FR;

Miroslav Vrana, Gent, BE;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A Network Processor includes a Fat Pipe Port and a memory sub-system that provides sufficient data to satisfy the Bandwidth requirements of the Fat Pipe Port. The memory sub-system includes a plurality of DDR DRAMs controlled so that data is extracted from one DDR DRAM or simultaneously from a plurality of the DDR DRAMs. By controlling the DDR DRAMs so that the outputs provide data serially or in parallel, the data Bandwidth is adjustable over a wide range. Similarly, data is written serially into one DDR DRAM or simultaneously into multiple DDR DRAMs. As a consequence buffers with data from the same frame are written into or read from different DDR DRAMs.


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