The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 2009
Filed:
Jan. 31, 2006
John A. Canaris, Albuquerque, NM (US);
Jorge Ernesto Carrillo, San Jose, CA (US);
Lester S. Sanders, Albuquerque, NM (US);
Yong Zhu, Albuquerque, NM (US);
John A. Canaris, Albuquerque, NM (US);
Jorge Ernesto Carrillo, San Jose, CA (US);
Lester S. Sanders, Albuquerque, NM (US);
Yong Zhu, Albuquerque, NM (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Methods and systems for building a simulation for verifying a design block, including efficient coordination of the control and validation of the operation of a first and second bus of the design block, with the first bus being an interface bus of a processor. An interface description is determined for a bus functional model of the interface bus of the processor. The interface description includes a synchronization bus for coordinating the bus functional model and a hardware description language (HDL) testbench. A hardware specification is generated that couples the first bus of the design block with the interface description, and couples the HDL testbench with the second bus of the design block and with the synchronization bus of the interface description. The simulation for verifying the design block is automatically generated from the bus functional model and the hardware specification.