The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2009

Filed:

Aug. 09, 2004
Applicants:

Rak-hwan Kim, Gyeonggi-do, KR;

Young-cheon Kim, Gyeonggi-do, KR;

Hyeon-deok Lee, Seoul, KR;

Hyun-young Kim, Seoul, KR;

In-sun Park, Gyeonggi-do, KR;

Inventors:

Rak-Hwan Kim, Gyeonggi-do, KR;

Young-Cheon Kim, Gyeonggi-do, KR;

Hyeon-Deok Lee, Seoul, KR;

Hyun-Young Kim, Seoul, KR;

In-Sun Park, Gyeonggi-do, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor memory device and a method of manufacturing the semiconductor memory device, in which a bit line can have a low resistance without an increase in the thickness of the bit line. In the semiconductor memory device, an insulating layer having a contact hole that exposes a conductive region is formed on a semiconductor substrate having the conductive region. A barrier metal layer is formed along the surface of the insulating layer and the surface of the contact hole. A grain control layer is formed between the barrier metal layer and the tungsten layer. A tungsten layer is formed on the grain control layer. A grain size of the tungsten layer is increased by the grain control layer.


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