The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7504718 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 17, 2009

Filed:

May. 10, 2005
Applicants:

Michael Anthony Gaynes, Vestal, NY (US);

Kathleen Conlon Hinge, Tarrytown, NY (US);

John Ulrich Knickerbocker, Wappingers Falls, NY (US);

Inventors:

Michael Anthony Gaynes, Vestal, NY (US);

Kathleen Conlon Hinge, Tarrytown, NY (US);

John Ulrich Knickerbocker, Wappingers Falls, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

Apparatus and methods are provided for constructing balanced semiconductor chip package structures that minimize bowing, in-plane strain and/or other thermally induced mechanical strains that may arise during thermal cycling, to thus prevent structural damage to chip package structures.


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Gaynes, Michael. (2009). Apparatus and methods for constructing balanced chip packages to reduce thermally induced mechanical strain (U.S. Patent No. 7504718). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7504718

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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