The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 2009
Filed:
Mar. 28, 2005
Elizabeth C. Glass, Gilbert, AZ (US);
Olin L. Hartin, Chandler, AZ (US);
Neil T. Tracht, Mesa, AZ (US);
Elizabeth C. Glass, Gilbert, AZ (US);
Olin L. Hartin, Chandler, AZ (US);
Neil T. Tracht, Mesa, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
Methods and apparatus are provided for RF switches (). In a preferred embodiment, the apparatus comprises one or more multi-gate n-channel enhancement mode FET transistors (). When used in pairs () each has its source () coupled to a first common RF I/O port () and drains coupled respectively to second and third RF I/O ports (), and gates (), coupled respectively to first and second control terminals (). The multi-gate regions () of the FETs () are parallel coupled, spaced-apart and serially arranged between source () and drain (). Lightly doped n-regions (Ldd, Lds) are provided serially arranged between the spaced-apart multi-gate regions (), the lightly doped n-regions (Ldd, Lds) being separated by more heavily doped n-regions (). Bias resistances () are provided between the sources () and control terminals () so as to provide a DC path between the control terminals () that maintains the source () voltage at the proper bias potential for enhancement mode operation.