The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2009

Filed:

May. 18, 2007
Applicants:

Mun-pyo Hong, Yongin, KR;

Woon-yong Park, Suwon, KR;

Jong-soo Yoon, Cheonan, KR;

Inventors:

Mun-Pyo Hong, Yongin, KR;

Woon-Yong Park, Suwon, KR;

Jong-Soo Yoon, Cheonan, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
Abstract

Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched. After depositing a passivation layer, a opening is formed by using the fourth mask and the exposed semiconductor layer through the opening is etched to separate the semiconductor layer under the adjacent data line.


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