The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2009

Filed:

Jun. 08, 2007
Applicants:

Futoshi Furuta, Kokubunji, JP;

Kazuo Saitoh, Kodaira, JP;

Inventors:

Futoshi Furuta, Kokubunji, JP;

Kazuo Saitoh, Kodaira, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 17/92 (2006.01);
U.S. Cl.
CPC ...
Abstract

Objects of the present invention are to provide an integration circuit which produces no integration leak so that the bit accuracy is improved in a sigma-delta modulation circuit or a delta modulator circuit, which is based on a single flux quantum circuit that uses a flux quantum as an information carrier, and to provide a method for reducing thermal noise and quantization noise. According to the present invention, an integration circuit is formed by Josephson junctions and an inductor to reduce the integration leak, and a plurality of modulator circuits are connected to one another so as to add up each output. As a result, it is possible to reduce the influence of thermal noise exerted upon the bit accuracy, the thermal noise having no correlativity to one another. Moreover, by changing the density or phase of a SFQ pulse to be supplied to the Josephson junctions of the integration circuit, the correlativity of quantization noise between the outputs of the modulator circuits is eliminated so that the bit accuracy is improved.


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