True/complement generator having relaxed setup time via self-resetting circuitry

Abstract

An integrated circuit includes a data node, an output node, and set logic coupling to the data node to the output node. The set logic changes a state of the output node in response to a change in state of the data node. The integrated circuit also includes a reset transistor, coupled to the data node, that resets the data node to a first state in response to a transition in a timing signal, an input transistor, coupled to the data node, that asserts the data node to a second state in response to receipt of a data signal, and reset logic coupled between the output node and the data node. The first reset logic resets the output node to an original state in response to resetting of the data node if the output node achieves a set state. The integrated circuit further includes feedback logic coupled between the output node and a reset input node of the reset logic that limits a duration of operation of the reset logic.