The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2009

Filed:

Mar. 28, 2007
Applicants:

Takashi Hamada, Kanagawa, JP;

Satoshi Murakami, Kanagawa, JP;

Shunpei Yamazaki, Tokyo, JP;

Osamu Nakamura, Kanagawa, JP;

Masayuki Kajiwara, Kanagawa, JP;

Junichi Koezuka, Kanagawa, JP;

Toru Takayama, Kanagawa, JP;

Inventors:

Takashi Hamada, Kanagawa, JP;

Satoshi Murakami, Kanagawa, JP;

Shunpei Yamazaki, Tokyo, JP;

Osamu Nakamura, Kanagawa, JP;

Masayuki Kajiwara, Kanagawa, JP;

Junichi Koezuka, Kanagawa, JP;

Toru Takayama, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/148 (2006.01); H01L 29/74 (2006.01); H01L 29/768 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention is characterized in that a semiconductor film containing a rare gas element is formed on a crystalline semiconductor film obtained by using a catalytic element via a barrier layer, and the catalytic element is moved from the crystalline semiconductor film to the semiconductor film containing a rare gas element by a heat treatment. Furthermore, a first impurity region and a second impurity region formed in a semiconductor layer of a first n-channel TFT are provided outside a gate electrode. A third impurity region formed in a semiconductor layer of a second n-channel TFT is provided so as to be partially overlapped with a gate electrode. A third impurity region is provided outside a gate electrode. A fourth impurity region formed in a semiconductor layer of a p-channel TFT is provided so as to be partially overlapped with a gate electrode. A fifth impurity region is provided outside a gate electrode.


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