The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 03, 2009
Filed:
Oct. 20, 2005
Richard Gerard Hofmann, Cary, NC (US);
James Norris Dieffenderfer, Apex, NC (US);
Thomas Sartorius, Raleigh, NC (US);
Thomas Philip Speier, Holly Springs, NC (US);
Jaya Prakash Subramaniam Ganasan, Youngsville, NC (US);
Richard Gerard Hofmann, Cary, NC (US);
James Norris Dieffenderfer, Apex, NC (US);
Thomas Sartorius, Raleigh, NC (US);
Thomas Philip Speier, Holly Springs, NC (US);
Jaya Prakash Subramaniam Ganasan, Youngsville, NC (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. A bus interconnect is configured to interface the processors to the memory devices. The bus interconnect is further configured to enforce an ordering constraint for a strongly-ordered memory access request from an originating processor to a target memory device by sending a memory barrier to each of the other memory devices accessible by the originating processor, except for those memory devices that the bus interconnect can confirm have no unexecuted memory access requests from the originating processor.