The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 03, 2009
Filed:
Feb. 02, 2005
David E. Tetzlaff, Minnetonka, MN (US);
F. Erich Goetting, Cupertino, CA (US);
Steven P. Young, Boulder, CO (US);
Marwan M. Hassoun, Austin, TX (US);
Moises E. Robinson, Austin, TX (US);
David E. Tetzlaff, Minnetonka, MN (US);
F. Erich Goetting, Cupertino, CA (US);
Steven P. Young, Boulder, CO (US);
Marwan M. Hassoun, Austin, TX (US);
Moises E. Robinson, Austin, TX (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
According to particular example embodiments, an integrated circuit includes one or more serializing data transmitters. Each such data transmitter is arranged to transmit data on a respective data output port of the integrated circuit, wherein the respective data output port for at least one of the data transmitters is dedicated to transmitting periodic data used for clocking a respective target circuit. In other particular embodiments involving feedback, phase-locked loop (PLL) signal control and/or delay-locked loop (DLL) signal control is achieved in functional blocks of a programmable logic device (PLD). The PLD is responsive to a source clock and includes a configurable logic array that includes configurable logic blocks and configurable routing blocks, and the respective data output port for at least one of the data transmitters provides a respective target clock.