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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7498839 B1

PDFFull Text
Date of Patent:
Mar. 03, 2009

Filed:

Oct. 22, 2004

Low power zones for programmable logic devices

Applicant:

Jesse H. Jenkins, Iv, Danville, CA (US);

Inventor:

Jesse H. Jenkins, IV, Danville, CA (US);

Assignee:

XILINX, Inc., San Jose, CA (US);

Attorneys:

William L. Paradice, III

John J. King

Primary Examiner:

Rexford Barnie

Assistant Examiner:

Dylan White

Int. Cl.
CPC ...
H03K 19/177 (2006.01); H03K 19/173 (2006.01); H01L 25/00 (2006.01); H01L 29/73 (2006.01); G06F 7/38 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit device such as a PLD is divided into a plurality of logic blocks, each including one or more resources of the device. The device includes a plurality of switch elements and a number of signal isolation circuits. The switch elements selectively disable corresponding logic blocks to reduce power consumption, and the signal isolation circuits selectively isolates corresponding logic blocks to prevent the transmission of invalid data from disabled logic blocks to enabled logic blocks.

Find Patent Forward Citations

Jenkins, IV, Jesse. (2009). Low power zones for programmable logic devices (U.S. Patent No. 7498839). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7498839

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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