The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 03, 2009
Filed:
Nov. 04, 2005
Arifur Rahman, San Jose, CA (US);
Sean W. Kao, Campbell, CA (US);
Tim Tuan, San Jose, CA (US);
Patrick J. Crotty, San Jose, CA (US);
Jinsong Oliver Huang, San Jose, CA (US);
Arifur Rahman, San Jose, CA (US);
Sean W. Kao, Campbell, CA (US);
Tim Tuan, San Jose, CA (US);
Patrick J. Crotty, San Jose, CA (US);
Jinsong Oliver Huang, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A PLD () includes a power management unit (PMU) that selectively implements one or more different power-reduction techniques in response to power configuration signals (PC). By manipulating the PC signals, the PMU can independently enable/disable various supply voltage circuits () that power CLBs (), IOBs (), and configuration memory cells (), can generate a capture signal that causes data stored in storage elements of the CLBs to be captured in configuration memory cells, and/or can switch power terminals of configuration memory cells between voltage supply circuits. Also, the PMU can sequentially apply and remove power from a number of configurable PLD portions in response to the PC signals, wherein each configurable portion may include any number of the PLD's resources.