The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 03, 2009
Filed:
Jan. 17, 2006
F. Erich Goetting, Cupertino, CA (US);
Trevor J. Bauer, Boulder, CO (US);
Patrick J. Mcguire, Cupertino, CA (US);
Bruce E. Talley, Louisville, CO (US);
Paul Ying-fung Wu, Saratoga, CA (US);
Steven P. Young, Boulder, CO (US);
F. Erich Goetting, Cupertino, CA (US);
Trevor J. Bauer, Boulder, CO (US);
Patrick J. McGuire, Cupertino, CA (US);
Bruce E. Talley, Louisville, CO (US);
Paul Ying-Fung Wu, Saratoga, CA (US);
Steven P. Young, Boulder, CO (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Methods of manufacturing a family of packaged integrated circuits (ICs) having at least two different logic capacities. A first IC die includes two different portions, of which at least one portion can be deliberately rendered non-operational in some manner (e.g., non-functional, inaccessible, and/or non-programmable) within the package. A first set of the first IC dies are packaged such that both portions of the dies are operational. A second set of the first IC dies are packaged such that only the first portion of each die is operational. Once the first and second sets are packaged and the second set of ICs has been evaluated, a decision is made whether or not to manufacture a second IC die that includes the first portion of the first die, while excluding the second portion.