The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2009

Filed:

Aug. 11, 2005
Applicants:

Andrew D. Huber, Poughkeepsie, NY (US);

Ciaran J. Brennan, Essex, VT (US);

Paul E. Dunn, Cambridge, VT (US);

Scott W. Gould, South Burlington, VT (US);

Lin Lin, Poughkeepsie, NY (US);

Erich C. Schanzenbach, Dover Plains, NY (US);

Inventors:

Andrew D. Huber, Poughkeepsie, NY (US);

Ciaran J. Brennan, Essex, VT (US);

Paul E. Dunn, Cambridge, VT (US);

Scott W. Gould, South Burlington, VT (US);

Lin Lin, Poughkeepsie, NY (US);

Erich C. Schanzenbach, Dover Plains, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated system and method to achieve ESD robustness on an integrated circuit (IC) in a fully automated ASIC design environment is described. Electrical characteristics and electrical limits on the power network are translated to power route region constraints for each chip input/output (I/O) cell. Electrical limits on the signal network are translated into signal route region constraints for each chip I/O cell. These constraints are passed on to an I/O floorplanner (automatic placer of I/O cells) that analyzes trade-offs between these constraints. For I/O cells that can not be placed to satisfy both power and signal region constraints, the I/O floorplanner utilizes the knowledge of alternative power distribution structures to group I/Os and create local power grid structures that have the effect of relaxing the power region constraints. Instructions for creating these local power grid structures are passed on to the automatic power routing tool.


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