The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2009

Filed:

Oct. 04, 2005
Applicants:

Jorn W. Janneck, San Jose, CA (US);

David B. Parlour, Pittsburgh, PA (US);

Inventors:

Jorn W. Janneck, San Jose, CA (US);

David B. Parlour, Pittsburgh, PA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Method and apparatus for implementing a program language description of a circuit design for an integrated circuit is described. In one example, a program is specified using a concurrent programming language. The program includes programming constructs that define a plurality of processes and a plurality of communication channels. A hierarchy of elements that classify the programming constructs of the program are generated to produce a transformed representation. A hardware description language (HDL) representation of the circuit design is generated from the transformed representation by translating the hierarchy of elements to a hierarchy of HDL constructs that implements the plurality of processes and the plurality of communication channels in hardware.


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