Method for optimizing of pipeline structure placement

Abstract

Using a computer and storage, a circuit design process is executed to preserve overall design quality while obtaining quality placements for a full class of pipeline structure signatures. These signatures include classic latch to latch pipelines, as well as a variety of latch to latch and mixed logic pipelines. The process employs a method for optimizing pipeline structure placement in a circuit design, by initiating an analysis of pipeline logic structures for correcting poor quality of result (QOR) placements by identifying poor placements caused by placement algorithmic response to degenerate cases and in the process of analysis preserving high quality placements of global placement and timing to preserve preponderant non-degenerate cases in said circuit design. Then employing a plurality of global placement steps, wherein each subsequent placement's quality of result (QOR) is dependent upon the prior placement's quality of result (QOR), circuits are identified as being involved in a class of degenerate cases, and circuits having poor placements are removed by unplacing them from the global placement solution and also other non-degenerate poor quality placements are corrected.