The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 2009
Filed:
Mar. 07, 2006
Conrad A. Theron, San Jose, CA (US);
Michael L. Simmons, Monte Sereno, CA (US);
Walter H. Edmondson, Morgan Hill, CA (US);
Mihai G. Statovici, Santa Barbara, CA (US);
Conrad A. Theron, San Jose, CA (US);
Michael L. Simmons, Monte Sereno, CA (US);
Walter H. Edmondson, Morgan Hill, CA (US);
Mihai G. Statovici, Santa Barbara, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Method, apparatus, and computer readable medium for generating test vectors for an integrated circuit (IC) under test is described. In one example, a test function is specified using at least one elementary function that encapsulates program code associated with an architecture of the IC under test. An engine is configured with device description data for the IC under test. The engine is executed with the test function as parametric input to generate the test vectors. In one example, the IC under test comprises a programmable logic device (PLD) and the test vectors include configuration data for configuring a pattern in the PLD and at least one test vector for exercising the pattern. The test vectors may be applied directly to the device or through automatic test equipment (ATE). Alternatively, the test vectors may be applied to a IC design simulation of the device.