The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 2009
Filed:
Nov. 23, 2005
Hitoshi Irino, Kanagawa, JP;
Hitoshi Irino, Kanagawa, JP;
NEC Electronics Corporation, Kanagawa, JP;
Abstract
To improve the ESD protection of a circuit receiving a signal. An inverter circuit INVis connected to ground wiring GNDfor supplying power, and is connected to power supply wiring VDDvia a PMOS transistor MP. An inverter circuit INVis connected to ground wiring GNDand power supply wiring VDDfor supplying power, and its input node is connected to an output node of the inverter circuit INV. Further, the ground wiring GNDand the ground wiring GNDare connected via a protection element PE. During normal operation, the output of an inverter circuit INVgoes to an H level, the output of an inverter circuit INVgoes to an L level, and the PMOS transistor MPis turned on. When ESD is applied, the power supply wiring VDDis place in a floating state, the output of the inverter circuit INVgoes to an H level, the PMOS transistor MPis turned off, and a current that occurs when EDS is applied does not flow into the inverter circuit INV
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile