The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 2009
Filed:
May. 31, 2005
Eisaku Maeda, Takatsuki, JP;
Akihiro Maejima, Takatsuki, JP;
Hiroki Matsunaga, Takatsuki, JP;
Jinsaku Kaneda, Suita, JP;
Masahiko Sasada, Fushimi-ku, JP;
Eisaku Maeda, Takatsuki, JP;
Akihiro Maejima, Takatsuki, JP;
Hiroki Matsunaga, Takatsuki, JP;
Jinsaku Kaneda, Suita, JP;
Masahiko Sasada, Fushimi-ku, JP;
Panasonic Corporation, Osaka, JP;
Abstract
The present invention relates to a layout of a multi-channel semiconductor integrated circuit and provides a layout of a semiconductor integrated circuit having ternary circuits in order to increase a degree of integration in the semiconductor integrated circuit and stabilize output characteristics. A ternary circuit is formed by arranging a second high-side transistor, a diode, a second level shift circuit on one hand, and a low-side transistor, a first high-side transistor, a first level shift circuit, and a pre-driver on the other, so that each of cells are arranged in a row and an output bonding pad is placed between the second high-side transistor and the low-side transistor, wherein a cell width of the first level shift circuit, second level shift circuit and pre-driver corresponds to a cell width of the low-side transistor.