The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 17, 2009
Filed:
Jun. 10, 2005
Jonathan Weiss, Lake Oswego, OR (US);
Jonathan Weiss, Lake Oswego, OR (US);
Other;
Abstract
A method for controlling crosstalk, power and yield in nanometer-technology integrated circuits ('ICs') is based on a performance driven space optimization technique that minimizes the coupling capacitance between the interconnecting wires. Given a routed IC design, virtual compression-springs are inserted between all the elements of the design creating a mesh of springs. The design is then perturbed, or shaken, by transforming the spring system into a minimum-energy problem, a solution for which reduces or eliminates crosstalk violations, minimizes power and increases yield as the springs reach minimum energy state. In a described method, the primitives of a given IC layout are defined in terms of object points. In a first step, a mesh of virtual compression springs connecting all the layout primitives is generated from the object points. The spring constant for each virtual spring embedded between interconnecting wires is chosen to follow a relationship between a slack function and the separation distance between the interconnecting wires. In a second step, the design is shaken by minimizing the energy of the virtual compression-spring-loaded-system, resulting in new object points and new positions for the springs and the interconnecting wires.