The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 17, 2009
Filed:
Mar. 24, 2006
Andre Sturm, Essex Junction, VT (US);
Christopher Miller, Underhill, VT (US);
Wolfgang Hokenmaier, Burlington, VT (US);
Michael Killian, Richmond, VT (US);
Jochen Hoffman, Colchester, VT (US);
Andre Sturm, Essex Junction, VT (US);
Christopher Miller, Underhill, VT (US);
Wolfgang Hokenmaier, Burlington, VT (US);
Michael Killian, Richmond, VT (US);
Jochen Hoffman, Colchester, VT (US);
Infineon Technologies AG, Neubiberg, DE;
Abstract
A method for reducing defect leakage current in a semiconductor memory device comprising a plurality of memory banks, each memory bank comprising a plurality of memory arrays and sense amplifier columns comprising a plurality of sense amplifiers, wherein there is a sense amplifier column positioned between and shared by memory arrays on opposites thereof. At least one bank-specific isolation control signal is independently generated for each of the plurality of memory banks depending on existence and location of an anomalous bitline leakage in a memory bank. The at least one bank-specific isolation control signal is supplied to at least one sense amplifier column in the corresponding memory bank to isolate at least one side to at least one memory array that is in an unselected state in a corresponding memory bank.