The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 17, 2009
Filed:
Jul. 24, 2006
Dima Prikhodko, Burlington, MA (US);
Sergey Nabokin, Pelham, NH (US);
Steven C. Sprinkle, Hampstead, NH (US);
Mikhail Shirokov, Methuen, MA (US);
Gene A. Tkachenko, Belmont, MA (US);
Jason Chiesa, Pelham, NH (US);
Dima Prikhodko, Burlington, MA (US);
Sergey Nabokin, Pelham, NH (US);
Steven C. Sprinkle, Hampstead, NH (US);
Mikhail Shirokov, Methuen, MA (US);
Gene A. Tkachenko, Belmont, MA (US);
Jason Chiesa, Pelham, NH (US);
Skyworks Solutions, Inc., Irvine, CA (US);
Abstract
According to one exemplary embodiment, a low harmonic switching device includes a first switching block including a first multi-gate FET, where the first switching block is coupled to a first input and a shared output of the low harmonic switching device. A first capacitor is coupled between a first gate and a source of the first multi-gate FET and a second capacitor is coupled between a second gate and a drain of the first multi-gate FET so as to cause a reduction in a harmonic amplitude in the shared output. A resistor can couple the source to the drain of the first multi-gate FET. The first switching block can further include a second multi-gate FET, where a source of the second multi-gate FET is coupled to the drain of the first multi-gate FET and a drain of the second multi-gate FET is coupled to the shared output.