The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 17, 2009
Filed:
Jan. 17, 2006
Steven P. Young, Boulder, CO (US);
Trevor J. Bauer, Boulder, CO (US);
F. Erich Goetting, Cupertino, CA (US);
P. Hugo Lamarche, Campbell, CA (US);
Patrick J. Mcguire, Cupertino, CA (US);
Kwansuhk OH, San Jose, CA (US);
Raymond C. Pang, San Jose, CA (US);
Bruce E. Talley, Louisville, CO (US);
Paul Ying-fung Wu, Saratoga, CA (US);
Steven P. Young, Boulder, CO (US);
Trevor J. Bauer, Boulder, CO (US);
F. Erich Goetting, Cupertino, CA (US);
P. Hugo Lamarche, Campbell, CA (US);
Patrick J. McGuire, Cupertino, CA (US);
Kwansuhk Oh, San Jose, CA (US);
Raymond C. Pang, San Jose, CA (US);
Bruce E. Talley, Louisville, CO (US);
Paul Ying-Fung Wu, Saratoga, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
An integrated circuit die (e.g., a programmable logic device (PLD) die) is manufactured that has the capability of being configured as at least two differently-sized family members. The IC die is tested prior to packaging. If a first portion of the IC die is fully functional, but a second portion includes a localized defect, then the IC die is packaged with a product selection code that configures the IC die to operate as only the first portion of the die. The second portion of the die is deliberately rendered non-operational. Therefore, the IC die can still be sold as a fully functional packaged IC.