The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 10, 2009
Filed:
Nov. 12, 2004
Applicant:
Benoit Payette, Blainville, CA;
Inventor:
Benoit Payette, Blainville, CA;
Assignee:
Xilinx, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H03K 17/693 (2006.01);
U.S. Cl.
CPC ...
Abstract
A reconfigurable module in a programmable logic device ('PLD'), such as a field-programmable gate array ('FPGA'), is reset after reconfiguration by an internal reset signal. The internal reset signal allows other modules in the PLD to remain active while the reconfigurable module is reconfigured and reset. The internal reset signal is generated by a reset manager circuit that optionally resides within the reconfigurable module.