The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 10, 2009
Filed:
Mar. 31, 2006
Christopher J. Gonzalez, Elmsford, NY (US);
Michael S. Gray, Fairfax, VT (US);
Matthew T. Guzowski, Essex Junction, VT (US);
Jason D. Hibbeler, Williston, VT (US);
Stephen I. Runyon, Pflugerville, TX (US);
Xiaoyun K. Wu, Hopewell Junction, NY (US);
Christopher J. Gonzalez, Elmsford, NY (US);
Michael S. Gray, Fairfax, VT (US);
Matthew T. Guzowski, Essex Junction, VT (US);
Jason D. Hibbeler, Williston, VT (US);
Stephen I. Runyon, Pflugerville, TX (US);
Xiaoyun K. Wu, Hopewell Junction, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of modifying a VLSI layout for performance optimization includes defining a revised set of ground rules for a plurality of original device shapes to be modified and flattening the plurality of original device shapes to a prime cell. A layout optimization operation is performed on the flattened device shapes, based on the revised set of ground rules, so as to create a plurality of revised device shapes. An overlay cell is then created from a difference between the revised device shapes and the original device shapes.